Energy Efficient Design of Four-operand Multiplier Architecture using CNTFET Technology

Authors N. Charmchi, M.R. Reshadinezhad
Affiliations

Faculty of Computer Engineering, University of Isfahan, 8174673441 Isfahan, Iran

Е-mail [email protected]
Issue Volume 10, Year 2018, Number 2
Dates Received 21 August 2017; revised manuscript received 28 April 2018; published online 29 April 2018
Citation N. Charmchi, M.R. Reshadinezhad, J. Nano- Electron. Phys. 10, No 2, 02022 (2018)
DOI https://doi.org/10.21272/jnep.10(2).02022
PACS Number(s) 84.30. − r, 85.35.Kt
Keywords Multi-operand multipliers, Fast multipliers, CNTFET nanotechnology multipliers, CNTFET full adders, Parallel multipliers.
Annotation

Multiplication is an essential part of digital arithmetic, due to its application in video and voice processing, FIR filters, cryptography and other related concepts. Reducing the power consumption and increasing the speed of multipliers will affect the performance of any VLSI system. An approach to accomplish the desired objective for the researchers is applying nano-technologies in implementing VLSI circuits. Carbon nanotube technology is an appropriate option among emerging nano-devices, due to its similarities to the preceding technology, MOSFET. Three new architectures are proposed for a four-bit four-operand multiplier. These multipliers and the conventional four-bit four-operand multiplier are designed, implemented and simulated through carbon nanotube field effect transistors. Evaluations and comparisons are run through HSPICE simulator, through using carbon nanotube technology. These multipliers outperform the common four-operand multiplication run on computers nowadays, referred to as conventional multiplier in this article.

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