Impact of Hole Density on Sub-10 nm SOI Trigate MOSFET Using Charge Plasma Technique with Circuit-Level Analysis

In this work, the charge plasma (CP) technique is employed to induce carriers in the undoped channel region of a Silicon-on-Insulator (SOI) trigate MOSFET, eliminating the need for conventional doping and reducing variability at nanoscale dimensions. A metal layer with a suitably engineered work function (WK) is incorporated beneath the channel to electrostatically induce carriers in the intrinsic silicon region, enabling efficient channel formation. The device performance is analyzed in terms of carrier distribution, surface potential profile, current–voltage (I-V) characteristics, and transconductance, along with circuit-level evaluation through Voltage Transfer Characteristics (VTC) of inverter configurations and stability assessment of 6T SRAM cells for a channel length of 10 nm. Simulations are carried out using Sentaurus TCAD with advanced physical models, including the Lombardi mobility model to account for surface scattering, Shockley–Read–Hall (SRH) and Auger recombination models for carrier recombination, and the Density-Gradient model to capture quantum confinement effects. The incorporation of a high-k dielectric significantly reduces leakage current and enhances electrostatic control. It is observed that Drain-Induced Barrier Lowering (DIBL) can be effectively suppressed and tuned by optimizing the work function of the metal layer beneath the channel. As a result of the CP implementation, the proposed device demonstrates a 16 % improvement in drain current compared to the conventional SOI MOSFET. Furthermore, the implemented 6T SRAM circuits exhibit a 28 % enhancement in hold static noise margin, indicating improved stability and reliability, thereby making the proposed CP-based SOI trigate MOSFET a strong candidate for future low-power and high-performance applications.