Leveraging Gate and Channel Engineering in Graphene Tunnel FET (GTFET) at Nano-Scale for Better Device Performance

This research work mainly focuses on various gate and channel engineering performed on typical tunnel field effect transistors (TFETs) at nano scale. This step-by-step development of typical nano device TFET model is showcased in this research work, in pursuit of better device performance. At first single gated homogenous dielectric i.e., SiO2 is used as oxide material, which further modified to dual gated heterogenous dielectric i.e. HfO2 – SiO2 combination in pursuit of better drive current (ION), and switching ratio (ION/IOFF). During this process simulation the intrinsic channel is developed as heterogeneous (InAs-Si) throughout the simulation. This results in considerable changes at surface potential distribution along the channel due to band-to-band-tunneling effect (BTBT). Secondly, this dual gated heterogeneous dielectric TFET is modified with 0-2 nm thin graphene layer, deployed over intrinsic channel. This nano-scaled graphene layer is introduced as nano-ribbon architecture, in order to reduce the tunable energy band gap. This expedites the BTBT tunneling across the junction and brings the turn on voltage (VON) much earlier, resulting fast digital switching. Lastly, this structure of TFET is further updated with dual metal, dual gated structure to investigate its ION/IOFF ratio and leakage current control. Silvaco TCAD is used to generate all related simulation work. Better drive current (ION) is achieved at 3.55  10 – 6 A/m with minimum leakage current (IOFF) of 2.16 10 – 16 A/m at 0.5 supply voltage (VDD) with minimum sub-threshold swing (SS) of 33.07 mV/decade.