Improvement Analysis of Leakage Currents with Stacked High-k/Metal Gate in 10 nm Strained Channel HOI FinFET
| Authors | Payal Kumari, Swagat Nanda , Priyanka Saha, Rudra Sankar Dhar |
| Affiliations |
Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, 796012 Aizawl, Mizoram, India |
| Е-mail | rdhar@uwaterloo.ca |
| Issue | Volume 14, Year 2022, Number 2 |
| Dates | Received 09 January 2022; revised manuscript received 16 April 2022; published online 29 April 2022 |
| Citation | Payal Kumari, Swagat Nanda, Priyanka Saha, Rudra Sankar Dhar, J. Nano- Electron. Phys. 14 No 2, 02004 (2022) |
| DOI | https://doi.org/10.21272/jnep.14(2).02004 |
| PACS Number(s) | 77.84.Bw |
| Keywords | Tri-gate FinFET (2) , Strained silicon, HOI structure, High-k dielectrics, Silvaco TCAD (3) , Short channel effects (5) . |
| Annotation |
In the current semiconductor scenario, multiple gate FETs like tri-gate (TG) FinFETs have been a boon to continue the scaling of devices below 32 nm technology. The application of strained silicon has further enhanced drive currents. Leakage currents have been reduced by employing high-k materials, which has led to enhanced device switching characteristics. The development and characterization of a 10 nm channel TG n-FinFET device incorporating a tri-layered strained silicon channel and stacked high-k dielectric materials as the gate oxide are the motivation of this paper. The electrical characteristics and short channel effects (SCEs) of all the devices have been determined by replacing the SiO2 gate oxide with a stacked gate oxide of 0.5 nm of SiO2 and 0.5 nm EOT of various high-k dielectric materials like ZrO2, Al2O3, Si3N4, and HfO2. It is observed that SCEs and leakage characteristics are significantly improved by the use of stacked high-k dielectric materials like HfO2, and the strain in the channel region significantly improves the drive current without hampering SCEs. Thus, the combination of strained silicon and HfO2 dielectrics showed improved performance of the developed device with a reduced chip area. |
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List of References |
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