Modelling and Implementation of Double Gate n-channel FET with Strain Engineered Tri-Layered Channel System for Enriched Drain Current

Authors Kuleen Kumar, Rudra Sankar Dhar , Swagat Nanda

Department of Electronics & Communication Engineering, National Institute of Technology Mizoram, Aizawl, 796012 Mizoram, India

Issue Volume 14, Year 2022, Number 2
Dates Received 21 December 2021; revised manuscript received 25 April 2022; published online 29 April 2022
Citation Kuleen Kumar, Rudra Sankar Dhar, Swagat Nanda, J. Nano- Electron. Phys. 14 No 2, 02028 (2022)
PACS Number(s) 73.23.Ad, 77.55.df
Keywords Strain silicon, Carrier quantum confinement, Ballistic transport, Nanoengineering, DG-SHOI FET devices.

The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscale devices by engineering the band structure arrangement. Leakage reduction while enhancing drain current is another major objective, therefore the development of a nano-regime double gate FET with a strained channel is perceived. So, implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Physics of the biaxial strain is studied and generated in the channel by inculcating three layers with optimal thicknesses, while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in the channel due to carrier quantum confinement, instigating ballistic transport across the 22 nm channel length device, leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56 % and transconductance amplification of 87.6 % are observed, while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.

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