Design and Analysis of Ternary D-Latch Using CNTFETs
| Authors | Anirban Banerjee, Vikash Prasad, Debaprasad Das |
| Affiliations |
Department of Electronics and Communication Engineering, Assam University, Silchar, India |
| Е-mail | dasdebaprasad@yahoo.com |
| Issue | Volume 11, Year 2019, Number 4 |
| Dates | Received 12 April 2019; revised manuscript received 01 August 2019; published online 22 August 2019 |
| Citation | Anirban Banerjee, Vikash Prasad, Debaprasad Das, J. Nano- Electron. Phys. 11 No 4, 04011 (2019) |
| DOI | https://doi.org/10.21272/jnep.11(4).04011 |
| PACS Number(s) | 85.30.Tv |
| Keywords | CNTFET (9) , MVL, Ternary, D-latch, Setup and hold time. |
| Annotation |
Integrated circuit (IC) chips are designed using binary logic. However, over the last two decades the complexity of IC chips has become manifold. This has resulted in large chip area due to large number of interconnections. Hence, large parasitics associated with the interconnections have reduced the speed and increased the power dissipation. These problems can be overcome using multi-value logic (MVL). To design digital circuits based on MVL, it is required to control the threshold voltage of the devices depending on the logic levels. Carbon nanotube field effect transistor (CNTFET) is one such emerging device which is suitable for MVL circuits as the threshold voltage of CNTFET can easily be controlled by changing the diameter of the carbon nanotubes (CNTs). The diameter of the carbon nanotube (CNT) is controlled by varying the chirality of the CNT. Ternary logic is one of the promising multi-value logics where there are three logic levels. In this paper, we have designed a D-latch based on ternary logic using CNTFET. The setup and hold times for the D-latch have been characterized. The delay and power have also been analyzed. |
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List of References |
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