Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits

Authors Anindya Jana1, Rajatsuvra Halder1, J.K. Sing2, Subir Kumar Sarkar1

1 Department of Electronics & Telecommunication Engineering, Jadavpur University, Kolkata-700032, India

2 Department of Computer Science and Engineering, Jadavpur University, Kolkata-700032, India

Issue Volume 4, Year 2012, Number 2
Dates Received 05 December 2012; revised manuscript received 24 April 2012; published online 07 May 2012
Citation Anindya Jana, Rajatsuvra Halder, J.K. Sing, Subir Kumar Sarkar, J. Nano-Electron. Phys. 4 No 2, 02004 (2012)
PACS Number(s) 85.35.G, 85.30.T
Keywords Single Electron Transistor (3) , CMOS (18) , Hybrid CMOS-SET Circuits (2) , MIB (2) , T-Spice (2) .
Annotation Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

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