Simulation and Finite Element Analysis of Electrical Characteristics of Gate-all-Around Junctionless Nanowire Transistors
| Authors | Neel Chatterjee , Sujata Pandey |
| Affiliations | Department of Electronics and Communication Engineering, Amity University Uttar Pradesh, Noida-201313, India |
| Е-mail | |
| Issue | Volume 8, Year 2016, Number 1 |
| Dates | Received 17 November 2015; published online 15 March 2016 |
| Citation | Neel Chatterjee, Sujata Pandey, J. Nano- Electron. Phys. 8 No 1, 01025 (2016) |
| DOI | 10.21272/jnep.8(1).01025 |
| PACS Number(s) | 62.23.Hj, 85.30.Tv, 07.05.Tp, 85.30. – z |
| Keywords | Nanowire (12) , Multiphysics, Current controllability. |
| Annotation | Gate all around nanowire transistors is one of the widely researched semiconductor devices, which has shown possibility of further miniaturization of semiconductor devices. This structure promises better current controllability and also lowers power consumption. In this paper, Silicon and Indium Antimonide based nanowire transistors have been designed and simulated using Multiphysics simulation software to investigate on its electrical properties. Simulations have been carried out to study band bending, drain current and current density inside the device for changing gate voltages. Further analytical model of the device is developed to explain the physical mechanism behind the operation of the device to support the simulation result. |
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