A Comparative Performance Study of Hybrid SET-CMOS Based Logic Circuits for the Estimation of Robustness
| Authors | Biswabandhu Jana1, Anindya Jana1, Jamuna Kanta Sing2, Subir Kumar Sarkar1 |
| Affiliations | 1 Department of Electronics and Telecommunication Engineering, Jadavpur University 2 Department of Computer Science and Engineering, Jadavpur University |
| Е-mail | |
| Issue | Volume 5, Year 2013, Number 3 |
| Dates | Received 15 February 2013; revised manuscript received 14 October 2013; published online 17 October 2013 |
| Citation | Biswabandhu Jana, Anindya Jana, Jamuna Kanta Sing, Subir Kumar Sarkar, J. Nano- Electron. Phys. 5 No 3, 03057 (2013) |
| DOI | |
| PACS Number(s) | 73.61.Cw |
| Keywords | Single electron transistor (SET), CMOS (19) , Hybrid CMOS-SET circuits (2) , MIB (2) , Noise margin (NM), T-Spice (2) . |
| Annotation | The urge of inventing a new low power consuming device for the post CMOS future technology has drawn the attention of the researchers on Single Electron Transistor [SET]. The two main virtues, ultra low power consumption [1] and ultra small dimension of SET [12, 13] have stimulated the researchers to consider it as a possible alternative. In our past paper [1] we have designed and simulated some basic gates. In this paper we have designed and simulated hybrid SET-CMOS based counter circuits, shift register to show that the hybrid SET-MOS based circuits consumes the lesser power than MOS based circuits. All the simulation were done and verified in Tanner environment using the MIB model for SET and the BSIM4.6.1 model for MOSFET. |
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