Resistance Based Drain Current Model of Surrounded Channel Junction Less Field Effect Transistor

A resistance based analytical model for drain current of a Junction less field effect transistor with surrounded channel (SCJLFET) is reported in this paper. Surrounded channel junction less field effect transistor (SCJLFET) exhibits the merits of both double and single gate Junction less field effect transistor. This paper illustrated the uses of resistance of the channel to obtain the drain current. The model is based on the concept that channel of a JLFET is comprised of either a space charge layer or a neutral layer or an accumulation layer or combination of any two of these layers. The model development starts with the formulation of resistances of these three types of layers followed by determination of total channel resistance in the four modes of operation of a JLFET. In the sub threshold mode only depletion layer is present while in bulk current mode total resistance is obtained by parallel combination of neutral semiconductor and depletion resistances. In flat band mode only neutral semiconductor layer is present while in accumulation mode total resistance is obtained by parallel combination of accumulation and depletion resistances. The drain current model in four modes is obtained by dividing the potential difference across the channel with the corresponding resistances of the modes. It is simplified model based on resistance of the body of the device. The model developed is fully analytical in nature which reduces the computation time in designing. The model is full range model applicable in all the operation modes of surrounded channel Junction less field effect transistor (SCJLFET). The potential expression also obtained using Poisson’s equation. The analytical drain current model has been verified with the help of TCAD numerical simulation results by comparing the transfer and output characteristics of the device obtained from TCAD and the drain current model.