An Analytical Approach of Threshold Voltage Model in Junctionless Field Effect Transistor with Hexagonal Shaped Cross-section
| Authors | P. Saikia, A.K. Raibaruah , K.C.D. Sarma |
| Affiliations |
Department of Instrumentation Engineering, Central Institute of Technology Kokrajhar, Kokrajhar BTAD, 783370 Assam, India |
| Е-mail | kcd.sarma@cit.ac.in |
| Issue | Volume 18, Year 2026, Number 5 |
| Dates | Received 20 June 2026; revised manuscript received 20 October 2026; published online 28 October 2026 |
| Citation | P. Saikia, A.K. Raibaruah, K.C.D. Sarma[footnoteRef:], J. Nano- Electron. Phys. 18 No 5, 05029 (2026) |
| DOI | https://doi.org/10.21272/jnep.18(5).05029 |
| PACS Number(s) | 85.30.Tv |
| Keywords | JLFET (8) , Hexagonal shaped, Depletion width, Threshold voltage (15) . |
| Annotation |
A novel Double Gate Junctionless Field Effect Transistor structure utilizing a hexagonal design is suggested in this paper. To evaluate the threshold voltage the depletion region width of a hexagonal junctionless transistor is first modeled. Here, 1D Poission’s equation is employed under partial depletion conditions. The device’s threshold voltage is determined using the device central potential throughout the channel length and the depletion region width. The generated model has been validated by comparing it with the results of TCAD simulations. For comparison, the threshold voltage variation with channel thickness, channel length, gate oxide thickness, dielectric constant of gate dielectric, temperature, drain to source voltage, and work function is studied. The comparison shows the closeness of the model with TCAD simulation results. |
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