An Improved Low Power Sense Amplifier Using Level Restoration Technique at 32 nm Technology
| Authors | Divya , Neha Goel , Renu Rani, Hashmat Usmani |
| Affiliations |
Department of ECE, Raj Kumar Goel Institute of Technology, Ghaziabad, India |
| Е-mail | divyaa.dutt13@gmail.com |
| Issue | Volume 17, Year 2025, Number 1 |
| Dates | Received 12 December 2024; revised manuscript received 16 February 2025; published online 27 February 2025 |
| Citation | Divya, Neha Goel, Renu Rani, Hashmat Usmani, J. Nano- Electron. Phys. 17 No 1, 01019 (2025) |
| DOI | https://doi.org/10.21272/jnep.17(1).01019 |
| PACS Number(s) | 85.40._e |
| Keywords | Sense amplifier, Level restoration, Sleep transistor, Delay (2) , Current (47) , Temperature (46) . |
| Annotation |
Sense amplifiers (SA) are essential in the peripheral circuitry of Static Random Access Memory (SRAM). They enhance operational speed, minimize power consumption, and reduce access time. This paper introduces a modified and enhanced Dual Switch Level Restoration Voltage-mode Sense Amplifier (DSLR-VMSA). An operational voltage of 1.8 V and a 32 nm technology node were used to simulate the designreveals DSLRA-SA's superior performance. Notably, this improved circuit achieves a power consumption of 6.7 uW, half that of the conventional Cross-Coupled Voltage Latch Sense Amplifier (CCVLSA). Energy and delay metrics also exhibit marked improvements. The study includes in-depth analyses such as Dimension and Temperature analyses, as well as evaluations on the impact of sleep transistors, to validate the enhanced SA's performance. Incorporating sleep transistors in the modified design further reduces power, delay, and energy consumption, significantly enhancing overall performance. The results underscore the suitability and superiority of the improved SA, particularly for low-power CMOS SRAM applications. |
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List of References |
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