Simulation and Performance Analysis of 32 nm FinFet based 4-Bit Carry Look Adder

Authors S. Rashid1, S. Khan2, A. Singh1,
Affiliations

1 Dept. of Electronics and Communication, Dr. A. P. J. Abdul Kalam Technical University, Lucknow

2 ME Department, Indian Institute of Technology Bombay, India

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Issue Volume 9, Year 2017, Number 5
Dates Received 16 June 2017; revised manuscript received 02 September 2017; published online 16 October 2017
Citation S. Rashid, S. Khan, A. Singh, J. Nano- Electron. Phys. 9 No 5, 05003 (2017)
DOI 10.21272/jnep.9(5).05003
PACS Number(s) 75.40.Mg, 84.30.Sk, 85.40.Ls
Keywords FinFET (12) , MOSFET (30) , ADDER (3) , 32 nm Technology, Power (22) , Speed (4) .
Annotation FinFET at 32 nm and beyond is an emerging transistor technology offer interesting delay–power tradeoff. FinFETs are a necessary step in the evolution of semiconductors because bulk CMOS has difficulties in scaling beyond 32 nm. Use of the back gate leads to very interesting design opportunities. Rich diversity of design styles, made possible by independent control of FinFET gates, can be used effectively to reduce total active power consumption IG/LP mode circuits provide an encouraging tradeoff between power and area. In the research work FinFET and MOSFET based adders are simulated as these devices are standout amongst the most generally actualized squares of microchip chips and advanced parts in the computerized incorporated circuit outline.

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