A New GAA FinFET without n-well or p-well

Authors A. Lazzaz1 , K. Bousbahi1,2 , M. Ghamnia1
Affiliations

1Laboratoire des Sciences de la Matière Condensée (LSMC), Université d’Oran 1, Oran, Algérie

2École supérieure en génie électrique et énergétique (ESGEE), Oran, Algérie

Е-mail lazzaz.abdelaziz@edu.univ-oran1.dz
Issue Volume 16, Year 2024, Number 2
Dates Received 21 January 2024; revised manuscript received 19 April 2023; published online 29 April 2023
Citation A. Lazzaz, K. Bousbahi, M. Ghamnia, J. Nano- Electron. Phys. 16 No 2, 02010 (2024)
DOI https://doi.org/10.21272/jnep.16(2).02010
PACS Number(s) 85.35.G, 85.30.T
Keywords FinFET (17) , Quantum effect, Leakage current (3) , CMOS (18) .
Annotation

The reduction in size of metal oxide semiconductor (MOS) devices results in the increase of leakage current due to Quantum effects. The different technologies proposed to overcome this problem. Variant structures of MOSFET such as Tri Gate FinFET or Pi gate and Omega gate to enhance current drive and control over the Short Channel Effects (SCE). In advanced technology node, the performance of CMOS circuits degrades. In sub 10 nm nodes technologies, FinFETs have a good channel control with high ON current (ION).Nowadays, power dissipation and leakage current are one the two crucial issues that the modern electronic industry is facing in 3 nm node technology. The other alternative devices such as novel GAA (Gate All Around) FinFET have been proposed to address these problems. This structure gained huge attention because of their possible fabrication process.In this paper, for the first time, we have investigated and simulated the different electrical characteristics of GAA FinFET 3 nm with N channel using HfO2 (high k material oxide) to improve the subthreshold characteristics. In the second part of this paper, we present a novel correction for the equations used in this technology because no n-well layer is required anymore as the device channel is totally surrounded by the gate which enables the placement of n and p devices in a CMOS gate much closer to each other than previous technologies.

List of References