High Temperature Effects on the Static Performance of 14 nm TG SOI N FinFET

The persistent scaling of feature sizes of metal–oxide–semiconductor field- effect transistors (MOSFETs) is described by Moore’s law which lead to the development of sophisticated electronic component technologies. Due to the difficulties in planar CMOS transistor scaling with the hope to preserve a good and acceptable channel control, FinFET devices have been introduced to overcome the different problems such as the increase of the leakage current, the decrease of the ON current and therefore the degradation of the performance ratio. FinFET devices have other important advantages over planar transistor such as reduced random doping fluctuation and the increase the threshold voltage. The BSIM Group continues to develop models for complementary metal–oxide–semiconductor technology by introducing device geometry-dependent, material-independent compact models which is essential for electronics designs.In this paper we investigate the effects of temperature variations from 77to 377K on the input and output characteristics of TG SOI N FinFET 14nm. The aim of the study is to find out how temperature affects the threshold voltage, the ON and OFF currents, the Subthreshold Swing (SS), the Drain Induced Barrier Lowering and the leakage current. The Berkeley PTM (Predictive Technology Model) is used in SPICE and TCAD Atlas tools. While increasing the temperature from 77to 377K, the degradation of the performance ratio ION/IOFF is observed.