Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

The intensive decrease of channel length for a MOS transistor imposes extensive constraints notably for controlling the short channel effects (SCEs) in nanoscale MOSFET. These constraints can degrade the device performance, hence determining the limits of miniaturization of MOSFET in nanoelectronics applications. In order to reduce the degree of SCEs, a number of new architectures have been reported. Due to their higher scaling capabilities, the double-gate (DG) MOSFETs are expected to be maintained in future nanoelectronics applications. However, with the continuous miniaturization other serious challenges related to the maximum power dissipation and the fabrication cost still persist owing to the high cost techniques used for the elaboration of the p-n junctions. Recently, a new design called junctionless MOSFET without source/drain junctions has been proposed to be an excellent alternative to the conventional MOSFET. The major advantage of this structure resides on the enhanced fabrication procedure through the elimination of the p-n junctions. In this work, the impact of channel length and high-k gate dielectrics materials on the subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs (JLTMCSG-MOSFETs) with high-k gate dielectrics and trial material (TM) structure has been studied using two-dimensional analytical model. This model is based on the solution of Poisson’s equation in continuous cylindrical regions using superposition method, where the Fourier-Bessel series and separation method have been used to obtain the accurate solution. The performance of low power JLTMCSG-MOSFETs is investigated in terms of surface potential distribution, electrical field, subthreshold current, drain induced barrier lowering (DIBL), subthreshold slope (SS) and threshold voltage (Vth). This study is carried out over a wide range of channel lengths and using high-k gate dielectrics. This study confirms that the analytical model used is useful not only for circuit simulations, but also for device design and optimization for both logic and analog RF circuits applications.