Activation Energy of Polycrystalline Silicon Thin Film Transistor
| Authors | Alka Panwar1 , Mahesh Chandra2, B.P. Tyagi2 |
| Affiliations | 1 Department of physics, Chinmaya Degree College, Haridwar – 249403, India 2 Department of Physics, D B S (Post Graduate) College, Dehradun – 248001, India |
| Е-mail | alkapanwar08@yahoo.com |
| Issue | Volume 3, Year 2011, Number 1, Part 4 |
| Dates | Received 04 February 2011, published online 17 October 2011 |
| Citation | Alka Panwar, Mahesh Chandra, B.P. Tyagi, J. Nano- Electron. Phys. 3 No1, 667 (2011) |
| DOI | |
| PACS Number(s) | 85.30 De |
| Keywords | Activation energy (7) , Polysilicon (2) , TFT (3) , Grain size (4) , Trap state density. |
| Annotation |
The activation energy of a poly-Si thin film transistor is observed to be influenced by the grain size, trap state density and the inversion layer thickness. The present study aims to investigate these parameters theoretically so as to explore optimum conditions for the working of a polycrystalline silicon thin film transistor. Our computations have revealed that the activation energy decreases with the increase of gate bias for all values of grain size, trap states density and the inversion layer thickness. These findings are compared with the experimental results. |
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List of References |
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