| Authors | Kunal Chakraborty1 , R. Narmadha2 , Islom Kadirov3 , DVSSSV Prasad4, Sireesha Koneru5, G. Deepika Reddy6 |
| Affiliations |
1Department of Electrical Engineering, IMPS College of Engineering and Technology, Malda, W.B, India 2Department of Mechatronics, Sathyabama Institute of Science and Technology, Chennai, T.N, India 3Department of Transport Systems, Urgench State University, Urgench, Uzbekistan 4Department of Mechanical Engineering, Aditya University, Surampalem, A.P, India 5Department of Mechanical Engineering, Koneru Lakshmaiah Education Foundation, Guntur, A.P, India 6Department of Mechanical Engineering, Govt. Polytechnic, Vaddepally, Telangana, India |
| Е-mail | kunal.eiilm.vu@gmail.com |
| Issue | Volume 18, Year 2026, Number 4 |
| Dates | Received 20 March 2026; revised manuscript received 15 August 2026; published online 21 August 2026 |
| Citation | Kunal Chakraborty, R. Narmadha, et al., J. Nano- Electron. Phys. 18 No 4, 04020 (2026) |
| DOI | https://doi.org/10.21272/jnep.18(4).04020 |
| PACS Number(s) | 88.40.jm, 88.40.H – |
| Keywords | Perovskite (6) , ETL (4) , HTL (4) , PV (32) , Thickness (13) , PCE (10) . |
| Annotation |
This research article showed a performance analysis of an FTO/ETL/Cs2SnBr6/HTL/Au-based PSC device using the SCAPS-1D simulator. To make an optimized PV device, three ETL mate-rials (CdS, SnO2, and ZnSe) and HTL materials (CBTS, P3HT, and CuO) have been used in the simulator. CdS-based ETL showed better performance at 80 nm thickness, where PCE achieved 25.14 %, and CBTS HTL material recorded an optimum PCE of 29.04 % at 60 nm thickness among all other used ETL and HTL materials. In a further look at optimized ETL and HTL, the Cs2SnBr6-based PSC has shown optimal photovoltaic performance at 500 nm thickness, where VOC, JSC, PCE, and FF values were recorded as 1.19 V, 32.12 mA/cm2, 27.66 %, and 62.4 %, respectively. Above 500 nm thickness of the Cs2SnBr6-based PSC, the device PV performance remained almost constant. On the other hand, it has been observed that between 10 °C-20 °C temperature, the PCE of the device increased significantly, and after 20 °C temperature, the PCE of the device does not change continuously. The optimized device temperature is 20 °C. All the simulation studies have been performed under the ambient temperature of 27 °C, and all the other recombination parameters have remained at ideal conditions. |
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