Carrier Mobility Analysis of Raised Source Drain Double Gate JLFET for Power Devices

The continuous downscaling of semiconductor devices has significantly influenced the evolution of advanced transistor architectures that are capable of ensuring high performance while minimizing short channel effects (SCEs). Among these novel structures the Raised Source Drain Double Gate Junctionless Field Effect Transistor (RSD DG JLFET), a junctionless device with elevated source and drain regions has attracted considerable attention due to its unique design and operational advantages. This device offers superior electrostatic control over the channel, reduced parasitic series resistance and enhanced carrier transport properties when compared with conventional MOSFETs and other junctionless devices. In this work a comprehensive carrier mobility analysis of RSD DG JLFET structures is carried out to investigate its suitability. The study systematically considers the influence of key physical parameters including the choice of dielectric material, dielectric thickness, gate work function and operating temperature. Using TCAD simulations the dependence of both electron and hole mobilities was evaluated along the longitudinal as well as transverse axes of the device. The results clearly demonstrate that the raised source drain configuration significantly mitigates parasitic resistances which are a major limitation in aggressively scaled devices. Furthermore, the structural modification also improves electrostatic integrity thereby boosting the overall device stability under varying bias conditions. Enhanced carrier mobility was observed which directly contributes to better current drive capability and reduced conduction losses. The findings suggest that RSD DG JLFET possess a promising balance between device scaling and performance reliability.