Impact of Device Sizing on Electrical Properties of DG-SOI-MOSFET Using Octave Software

Authors M. Djerioui1, M. Hebali2 , M. Abboun Abid3

1ENS Ouargla, 300000 Ouargla, Algeria

2Department of Electrotechnical, University Mustapha STAMBOULI of Mascara, 29000 Mascara, Algeria

3ENP Oran, B.P 1523 Oran El M’Naouar, 31000 Oran, Algeria

Issue Volume 14, Year 2022, Number 5
Dates Received 20 June 2022; revised manuscript received 24 October 2022; published online 28 October 2022
Citation M. Djerioui, M. Hebali, M. Abboun Abid, J. Nano- Electron. Phys. 14 No 5, 05025 (2022)
PACS Number(s) 85.30.De
Keywords Symmetrical DG-SOI-MOSFET, Electrical characteristic, Conductance (4) , Miniaturization, (2558) .

Double-gate (DG) SOI-MOSFET device is regarded as the next generation of VLSI circuits. In this paper, we show the impact of miniaturization on the demand and challenges of the undoped-body symmetric DG-SOI-MOSFET planar design for low power and high performance. By exploiting the graphical approach used previously, which consists of numerical simulations valid for all bias conditions, from sub-threshold to strong inversion and from linear to saturation operation, we visualized the evolution of the transfer, output and electrical characteristics and output conductance by varying each of the parameters independently: oxide thickness (tox), channel length (L) and channel width (W). The results obtained allowed to verify how each dimension affects different electrical properties of the DG-SOI-MOSFET. It was found that L, W and tox significantly influence these properties, as well as this transistor includes the channel length-modulation (CLM) and drain induced barrier lowering (DIBL) effects. This study showed the ability to predict the electrical behavior of the DG-SOI-MOSFET by its geometrical dimensions, and the possibility of choosing the optimal dimensions to ensure high performance of this transistor in both analog and digital circuits.

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