The Study of Hetero Dielectric Buried Oxide and Heterojunction Dual Material TFET

Authors P. Vimala , Bhoomi Reddy Venkata Sravanthi Reddy, Shreyas Yadav V.R, Suprith C

Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering,Bangalore, India

Issue Volume 14, Year 2022, Number 4
Dates Received 11 June 2022; revised manuscript received 08 August 2022; published online 25 August 2022
Citation P. Vimala, Bhoomi Reddy Venkata Sravanthi Reddy, Shreyas Yadav V.R, Suprith C., J. Nano- Electron. Phys. 14 No 4, 04009 (2022)
PACS Number(s) 72.80.Vp, 85.30.Tv
Keywords Heterojunction (6) , Dual material, Tunnel FET (2) , Drain current (3) .

This study aims to enhance the ambipolar behavior and low-ON current of hetero dielectric BOX and heterojunction dual material TFETs. Tunnel FETs (TFETs), which work on tunnelling phenomenon, can circumvent MOSFET limitations owing to device scalability. Subthreshold current, drain-induced barrier lowering, and hot electron effects are among MOSFET restrictions owing to device scaling. TFET does not fulfil the ITRS requirement for a high ON current, which is compatible with MOSFET-based circuits. Different structures, channel materials, gate oxide materials, and appropriate gate work-functions can be used to improve the low ON current of TFETs. We propose and develop a heterojunction dual material TFET in this study. Heterojunction double gate TFET has been studied previously. The ON-state current is improved and the ambipolar current is reduced compared to the standard TFET, increasing the ON-state current lowers the subthreshold slope. Also, the dual gate TFET has higher performance than conventional TFET. The addition of heterojunction to the device aids in the reduction of the band gap at the source channel junction, and the gate oxide and junction work together to increase drain current (ID) capacity while lowering parasitic strength. The concept of hetero buried oxide along with heterojunction dual material is integrated together for better outcomes. Initially the surface potential is derived using Poison’s equation divided equally for regions of buried oxide as SiO2 and HfO2. Lateral and vertical electric fields are implemented using the surface potential and the potential along the Y-axis. The source material is InGaAs, the target material is InP and SiO2/high-k hetero dielectric is used as the gate oxide material. Simulation is done with SILVACO TCAD.

List of References