Low Noise Amplifier Design with Current Reuse Architecture and Pre-distortion Technique for Nanoelectronic Sensors Operating at 2.4 GHz

Authors K. Suganthi1, B. Venila2, M.S. Abirami3, Ritam Dutta4

1Department of ECE, SRMIST, Chennai 603203 Tamil Nadu, India

2Department of Mathematics, SRMIST, Chennai 603203 Tamil Nadu, India

3Department of Computational Intelligence, SRMIST, Chennai 603203 Tamil Nadu, India

4CISR – ITER, Siksha ‘O’ Anusandhan University, Bhubaneswar 751030 Odisha, India

Е-mail ritamdutta1986@gmail.com
Issue Volume 14, Year 2022, Number 3
Dates Received 24 May 2022; revised manuscript received 22 June 2022; published online 30 June 2022
Citation K. Suganthi, B. Venila, M.S. Abirami, et al., J. Nano- Electron. Phys. 14 No 3, 03006 (2022)
DOI https://doi.org/10.21272/jnep.14(3).03006
PACS Number(s) 85.35. – p
Keywords CMOS design, LNA (2) , Nanoamplifier, Circuit design, Nanosensing nanomaterials.

This paper describes the development of different CMOS Low Noise Amplifier (LNA) topologies for achieving high linearity and low noise for nanosensor designs. The frequency of operation is 2.4 GHz, the ISM band is suitable for nanosensor applications. The novelty is introduced with a reconfigurable structure with the current reuse architecture for low power consumption, and pre-distortion technique is utilized to achieve good linearity without distortions, which is a preferrable metric for amplifier design. Nanoscale designs are achieved with an increase in robustness. The proposed CMOS based LNA design has moderate gain with a low noise figure of 2.6 dB at 2.4 GHz and less than 2 dB at 5 GHz. Good reverse isolation is achieved by the Voltage Standing Wave Ratio (VSWR), and the optimized S parameter input and output reflection coefficients are less than – 10 dB. The stability of the designed amplifier and the power gain results are compatible with the nanosensor design. The novelty achieved in the design is thewide bandwidth, good Figure of Merit (FOM), small size, moderate gain without distortions, low noise and good linearity due to complex design. Also, the power gain is moderate, and the layout of the design occupies a small chip area of 0.5×0.2 mm2.

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