CMOS Cascode Low Noise Amplifier (CCLNA) Design for Nanosensor Applications

Authors K. Suganthi1, S. Malarvizhi1, Ritam Dutta2

1Department of ECE, SRMIST, Chennai – 603203 Tamil Nadu, India

2CISR – ITER, Siksha ‘O’ Anusandhan University, Bhubaneswar – 751030 Odisha, India

Issue Volume 14, Year 2022, Number 3
Dates Received 15 February 2022; revised manuscript received 24 June 2022; published online 30 July 2022
Citation K. Suganthi, S. Malarvizhi, Ritam Dutta, J. Nano- Electron. Phys. 14 No 3, 03020 (2022)
PACS Number(s) 84.40.Lj
Keywords CCLNA, VSWR (2) , RADAR (2) , Conversion gain, CMOS design, Nanosensing, Nanomaterials (4) .

A design of Cascode Low Noise Amplifier (CCLNA) circuit is proposed using standard 0.18 µm millimeter wave (mmW) CMOS technology. The proposed CMOS CCLNA circuit has achieved a maximum conversion gain of 17.4 dB, NF of dB and a power of 22.3 mW at mmW Ka band. The input and output reflection coefficients are well matched with less than – 10 dB at the Ka band frequency with good Voltage Standing Wave Ratio (VSWR). The reverse transmission coefficient S12 is less than – 12 dB, indicating that the LNA has improved isolation between input and output, the stability factor is greater than one for the amplifier realization. The SoC-based CCLNA design for circuit level examination with analytical equations also proved that the simulation outcomes were prone to the design suitable for nanoelectronic applications for an output power of 2 dBm, transition frequency (fT) of 64 GHz and maximum operation frequency (fmax) of 96 GHz, which significantly shows the efficiency of the proposed method suitable for nanosensor applications. The justification of Radio Detection and Ranging (RADAR) front end simulation performance validates that the receiver designed with proposed LNA is suitable for the receiver design at high mmW frequencies.

List of References