Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip

Authors S. Nanda, R.S. Dhar

Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, 796012 Aizawl, India

Е-mail rdhar@uwaterloo.ca
Issue Volume 13, Year 2021, Number 3
Dates Received 11 January 2021; revised manuscript received 14 June 2021; published online 25 June 2021
Citation S. Nanda, R.S. Dhar, J. Nano- Electron. Phys. 13 No 3, 03015 (2021)
DOI https://doi.org/10.21272/jnep.13(3).03015
PACS Number(s) 85.75.Hh
Keywords High-k dielectric materials, TG SOI FinFETs, Silvaco TCAD (3) , EOT (3) .

While entering the era of More than Moore by reducing the geometrical dimensions for FET devices to accommodate more components on a single chip, short channel effects (SCEs) like higher leakage currents, Drain Induced Barrier lowering (DIBL), etc., create a major hindrance. Employing high-k dielectrics as gate oxide is being a meticulous approach today on attaining an enhanced device. The objective of this work is to develop and characterize a 14 nm gate length Tri-Gate n-FinFET device and compare the effects of short channel parameters. This is achieved by replacing the SiO2 gate oxide with various high-k dielectric materials like Si3N4, Al2O3, ZrO2 and HfO2. Here, the 14 nm gate length Tri-Gate n-FinFET device is developed and modelled using SILVACO TCAD tools. The SOI structure is also implemented here for betterment in device performance. Multiple devices are developed with varied gate oxides of SiO2 and other high-k dielectrics like Si3N4, Al2O3, ZrO2 and HfO2 as the gate dielectric material considering the equivalent oxide thickness calculation on the same structure. The short channel device parameters such as threshold voltage, Ion current, Ioff current, subthreshold slope, DIBL, and Ion/Ioff current ratio were systematically analyzed for different devices. The comparison of different developed devices showed that the Ion current was almost the same for all the devices. However, the Ioff current reduced with increasing dielectric constants thereby increasing the Ion/Ioff ratio which led to lower leakage currents and better device performance. Similarly, the devices which comprised of higher dielectric constants had lower subthreshold swings and lower DIBL values leading to reduction in SCEs. Thus, the 14 nm gate length Tri-Gate n-FinFET device was developed and modelled successfully, and the results showed improved SCEs of the developed device by using HfO2 dielectrics with reduced chip area.

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