Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications
| Authors | Ritam Dutta1,2, Nitai Paitya2 |
| Affiliations |
1Surendra Institute of Engineering & Management, MAKAUT, West Bengal 734009, India 2Sikkim Manipal Institute of Technology, SMU, Sikkim 737136, India |
| Е-mail | ritamdutta1986@gmail.com |
| Issue | Volume 13, Year 2021, Number 3 |
| Dates | Received 10 January 2021; revised manuscript received 10 June 2021; published online 25 June 2021 |
| Citation | Ritam Dutta, Nitai Paitya, J. Nano- Electron. Phys. 13 No 3, 03020 (2021) |
| DOI | https://doi.org/10.21272/jnep.13(3).03020 |
| PACS Number(s) | 85.30.De |
| Keywords | Work function (2) , DG-TM-PiN-TGNFET, III/V Compound material, Surface potential (9) , Reverse tunneling, TCAD (11) . |
| Annotation |
Influence of triple material having different work functions have been designed and investigated on a double gated P-i-N tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) for improved device performance. A III/V compound material (InAs) has been used in the source region for this n-channel heterojunction tunnel FET, because of which stress – strain effect results better tunneling. Graphene, being a low band gap material, has been used as nano ribbon to tune suitably the energy bandgap as less as possible. In this paper, the three different materials are introduced to restrict the drain – source reverse tunneling and also improve the TFET device performance in terms of surface potential distribution, lateral – vertical electric field variation and transfer characteristics. This triple material-based DG-PiN-TGNFET structure provides better subthreshold swing of 18.56 mV/decade at 0.5 V supply voltage compared to single and double material based double gated TGN-FET structures. The entire simulation has been performed using two-dimensional mathematical TCAD device software. Moreover, the low threshold voltage encourages the proposed device best suitable for low power logic applications. |
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List of References |
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