An Ultra-low Power, High SNM, High Speed and High Temperature of 6T-SRAM Cell in 3C-SiC 130 nm CMOS Technology
| Authors | D. Berbara1,2, M. Abboun Abid2, M. Hebali2,3, M. Benzohra4, D. Chalabi2 |
| Affiliations |
1University Center Ahmed ben Yahia El-wancharissi of Tissemsilt, 38000 Tissemsilt, Algeria 2Laboratory: CaSiCCE, ENP Oran-M.A., 31000 Oran, Algeria 3Department of Electrotechnical, University Mustapha Stambouli of Mascara, 29000 Mascara, Algeria 4Department of Networking and Telecommunications, University of Rouen, Laboratory LECAP, 7600, France |
| Е-mail | mourad.hebali@univ-mascara.dz |
| Issue | Volume 12, Year 2020, Number 4 |
| Dates | Received 16 March 2020; revised manuscript received 15 August 2020; published online 25 August 2020 |
| Citation | D. Berbara, M. Abboun Abid, M. Hebali, et al., J. Nano- Electron. Phys. 12 No 4, 04024 (2020) |
| DOI | https://doi.org/10.21272/jnep.12(4).04024 |
| PACS Number(s) | 85.75.Bb, 85.70. – w, 85.75. – d |
| Keywords | 3C-SiC (2) , BSIM3v3 (2) , CMOS (18) , 130 nm technology, SRAM (4) . |
| Annotation |
Semiconductor memories are becoming more and more present in the most hostile environments. In this paper, the electrical behavior of the 6T-SRAM memory cell in 3C-SiC in 130 nm CMOS technology was studied. The study of the effect of the cell ratio (CR), supply voltage (VDD) and temperature (T) on the static noise margin (SNM), as well as the influence of temperature on write time showed that this cell is characterized by a low power P 27 nW, a high speed (write time τwrite 0.305 ns) and a wide noise margin RSNM 320 mV, and also it works under a low voltage VDD 1.2 V and a high temperature up to 350 °C. The comparison with the literature has shown that the 6T-SRAM cell in SiC with 130 nm CMOS technology is characterized by good electrical behavior and high electrical performance. |
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List of References |
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