Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor

Authors Manjula Vijh1,2 , R.S. Gupta3 , Sujata Pandey4
Affiliations

1 Amity University Uttar Pradesh, Noida, India

2 Amity School of Engineering and Technology, New Delhi, India

3 Maharaja Agrasen Institute of Technology, New Delhi, India

4 Amity Institute of Telecom Engineering and Management, Amity University Uttar Pradesh, Noida, India

Е-mail [email protected]
Issue Volume 9, Year 2017, Number 1
Dates Received 06 December 2016; revised manuscript received 08 February 2017; published online 20 February 2017
Citation Manjula Vijh, R.S. Gupta, Sujata Pandey, J. Nano- Electron. Phys. 9 No 1, 01030 (2017)
DOI 10.21272/jnep.9(1).01030
PACS Number(s) 67.72.uj, 61.82.Fk, 71.55.Eq,85.30.De
Keywords Surrounding gate Tunnel FET, Heterojunction (6) , Surface Potential (9) , Threshold Voltage (15) , Broken-gap (2) .
Annotation Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device, due to its varied advantages, is considered in applications where devices are scaled down to deep sub-micron level. Like MOSFETs, many geometries of TFETs have been studied and analyzed in the past few years. This work, presents a two dimensional analytical model for a III-V Heterojunction Surrounding Gate Tunneling Field Effect Transistor. 2-D Poisson’s equation in cylindrical coordinates has been solved to derive the expression of Surface Potential and threshold voltage of the device. A broken gap GaSb/InAs heterostructure has been considered in this work. Variation of potential profiles are shown with different gate and drain biases, by varying radius of the transistor,and different gate metals. Also, variation of threshold voltage is shown with respect to channel length and radius of the nanowire.

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