Design Device for Subthreshold Slope in DG Fully Depleted SOI MOSFET

Authors Neha Goel1 , Manoj Kumar Pandey2
Affiliations

1 Research Scholar, SRM University NCR Campus Ghaziabad, India

2 Department of ECE, SRM University NCR Campus Ghaziabad, India

Е-mail [email protected], [email protected]
Issue Volume 9, Year 2017, Number 1
Dates Received 24 October 2016; revised manuscript received 07 February 2017; published online 20 February 2017
Citation Neha Goel, Manoj Kumar Pandey, J. Nano- Electron. Phys. 9 No 1, 01022 (2017)
DOI 10.21272/jnep.9(1).01022
PACS Number(s) 85.30.De
Keywords Fully depleted silicon on insulator (FDSOI) (2) , Threshold voltage (15) , Sub threshold slope.
Annotation In this paper, we discuss how a short channel effects can be suppressed and how a threshold voltage fluctuation can be minimized and better control of subthreshold slope by the impact of the back gate bias and control of gate work function of a fully depleted SOI (Silicon-On-Insulator) MOSFET. The fluctuation in the threshold voltage and subthreshold slope are due to short channel effects. The Back gate voltage plays a significant role on the threshold voltage and thin buried oxide is used to suppress the short-channel effects and is used to keep a low value of the subthreshold slope are described in this paper. It is shown that how short channel effects can be suppressed in order to improve subthreshold slope.

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