Numerical Simulation and Mathematical Modeling of 3D DG SOI MOSFET with the Influence of Biasing with Back Gate
| Authors | Neha Goel1, Manoj Kumar Pandey2 |
| Affiliations | 1 Research Scholar, SRM University, NCR Campus Ghaziabad, India 2 Department of ECE, SRM University NCR Campus Ghaziabad, India |
| Е-mail | |
| Issue | Volume 9, Year 2017, Number 5 |
| Dates | Received 20 June 2017; revised manuscript received 20 June 2017; published online 16 October 2017 |
| Citation | Neha Goel, Manoj Kumar Pandey, J. Nano- Electron. Phys. 9 No 5, 05002 (2017) |
| DOI | 10.21272/jnep.9(5).05002 |
| PACS Number(s) | 85.30.tv |
| Keywords | Fully Depleted Silicon on insulator (FDSOI) (2) , 3D analytical model, Short channel effects (SCE), Bulk CMOS, Surface potential (9) , Threshold voltage (15) , Drain induced barrier lowering (DIBL). |
| Annotation | Design consideration of a fully depleted SOI (Silicon-On-Insulator) MOSFET device by three dimensional mathematical modeling is presented in this paper. To the best of our knowledge, when our device is fabricated in nanometer regime, the threshold voltage changes due to various effects. Back gate voltage plays a significant role on the controlling of threshold voltage. Separation of variable is used to solve the Poisson’s three dimensional equation, analytically with suitable boundary conditions for the threshold voltage of double gate SOI MOSFET with the influence of biasing with back gate. In this work, changes in threshold voltage has been calculated and demonstrated that how short channel effects and DIBL can be suppressed with application of Back Gate bias voltage |
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