Performance Estimation of Recessed Modified Junctionless Multigate Transistor

Scaling has been instrumental in improving speed and power consumption. Moore's law insists on a constant periodic decrease in the size of devices. Gate dielectric engineering is one of the means to reduce the size of devices. This paper describes the simulation of the electrical characteristics of a reduced channel width and an increased dielectric thickness at the gate edges of a junctionless multigate transistor. The novelty of the work is the increased gate oxide thickness at the edges that reduces the leakage current. HfO2 is used as a dielectric material because thin SiO2 layer causes leakage through the gate oxide and into the channel. The excellent property of HfO2 is its high dielectric constant value (20-25), which is 4 to 6 times higher than of SiO2. In this work, the performance parameters of a double-gate junctionless FET, namely the threshold voltage (Vth), OFF-current, ON-current, ON-to-OFF current ratio, and subthreshold swing (SS), have been investigated for the gate work function window from 4.6 to 5.0 eV. In the work function window, optimal performance has been found for a gate work function of 4.9 eV. The proposed device has low IOFF and subthreshold swing when compared to conventional junctionless FET. This paper presents the simulation of a junctionless transistor using Atlas Silvaco TCAD tool. The device shows OFF-current of the order of 10 ^– 16 A/(m, ON-to-OFF current ratio of the order of 10¹¹ and subthreshold swing of 59.78 mV/dec. The device shows constant subthreshold swing for the work function range of 4.6 to 5.0 eV. The simulation results show that the proposed device is suitable for low power applications.