Temperature and Geometric Scaling Effects on CMOS Inverter Performance: A Static and Dynamic Parametric Analysis
| Authors | Y. Chebabhi1, A. Dendouga1, B. Lakehal2, S. Kouda3 |
| Affiliations |
1Advanced Electronics Laboratory LEA Electronics Department, University of Batna 2 Algeria, Batna 2Department of Industrial Safety, Health and Safety Institute, University of Batna 2, Fesdis, Batna 05078, Algeria 3LEREESI, Laboratory Higher National School of Renewable Energy, Environment and Sustainable Development, University of Batna 2 Algeria, Batna |
| Е-mail | lakehalbra@gmail.com |
| Issue | Volume 17, Year 2025, Number 6 |
| Dates | Received 06 October 2025; revised manuscript received 14 December 2025; published online 19 December 2025 |
| Citation | Y. Chebabhi, A. Dendouga, B. Lakehal, et al., J. Nano- Electron. Phys. 17 No 6, 06007 (2025) |
| DOI | https://doi.org/10.21272/jnep.17(6).06007 |
| PACS Number(s) | 85.30.De, 85.40.Qx, 73.40.Qv |
| Keywords | CMOS inverter, Temperature stability, Channel scaling, Static/Dynamic analysis. |
| Annotation |
Timing analysis serves as a cornerstone in VLSI design methodology, directly influencing both performance metrics and energy efficiency. The calculation of signal transition delays holds significant research importance due to its impact on overall system characteristics. This study investigates the fundamental mechanisms governing static and dynamic CMOS inverter operations. To measure device behavior, we look at important indicators such as voltage transfer curves, saturation voltage, peak drain current (ID peak), delay, and rise/fall times. And how to control it. This study examines the effects of scaled channel sizes (90-360 nm length, 120-1200 nm width) and extreme temperatures (– 108°C to 270 °C). The findings indicate that performance is significantly altered by thermal and geometric shifts; for instance, the ID peak decreases from 17.05 A at – 108 °C to 7.76 A at 189 °C, and reduced channels shift the switching threshold. We map the combined effect of NMOS and PMOS responses on power-delay trade-offs using CADENCE Virtuoso. Resilient CMOS design for a range of operating conditions and process tolerances is guided by these insights. |
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List of References |
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