Impact of the High-K Dielectric Material as Spacer on Analog and RF Performance of the GS-DG-FinFET

Authors A. Pattnaik, Sruti S. Singh, S.K. Mohapatra
Affiliations

School Electronics Engineering, KIIT University, Bhubaneswar, India

Е-mail asmita027@gmail.com
Issue Volume 11, Year 2019, Number 6
Dates Received 27 July 2019; revised manuscript received 05 December 2019; published online 13 December 2019
Citation A. Pattnaik, Sruti S. Singh, S.K. Mohapatra, J. Nano- Electron. Phys. 11 No 6, 06028 (2019)
DOI https://doi.org/10.21272/jnep.11(6).06028
PACS Number(s) 61.46. – w, 64.70.Nd, 81.07. – b, 85.30.De, 85.30.Tv
Keywords Gate stack-double gate-FinFET, Spacer engineering, Intrinsic capacitances, High-K (8) , SCEs (4) .
Annotation

In multi-gate technology, the DG-FinFET is an emerging structure due to its better electrostatic control over the channel. This paper shows a systematic study of the structure, double gate (DG) FinFET, which has been modified using the high-K dielectric material as the gate stack (GS) and spacer engineering which is going to boost its properties. The analyzed SCEs are sub-threshold slope (SS), drain induced barrier lowering (DIBL), and the switching current ratio (ION/IOFF ratio). The analog performance of the devices is studied on the basis of parameters are transconductance (gm), trans-conductance gain factor (TGF), the output conductance (gd), drain current (ID), early voltage (VEA), intrinsic gain (AV). The RF performance is analyzed on the merits of parasitic gate capacitance (Cgd, Cgs and Cgg), cutoff frequency (fT), gain frequency product (GFP), and transconductance frequency product (TFP). With this we intended to provide a comparative study to suggest the possibility for better performance of the GS-DG structure at VDS ( 0.05 V and 1.0 V. Here, DIBL exhibits 49.8 % and SS value is decreased by 32.65 %. For the analog performance study, the VEA is raised by 4.31 %, the TGF of the device is improved by 33.9 % and the gain has been also improved as compared to the conventional one. The simulation is carried out considering 45 nm node parameters according to the ITRS road map for the high-speed applications and low power consuming circuits.

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