Electrical Сharacterization of Ge-FinFET Transistor Based on Nanoscale Channel Dimensions

Authors Ahmed Mahmood1, Waheb A. Jabbar1 , Yasir Hashim2, Hadi Bin Manap1

1Faculty of Engineering Technology, University Malaysia Pahang, 26300 Gambang, Kuantan, Pahang, Malaysia

2Computer Engineering Department, Faculty of Engineering, Ishik University, Erbil-Kurdistan, Iraq

Е-mail waheb@ieee.org
Issue Volume 11, Year 2019, Number 1
Dates Received 19 November 2018; revised manuscript received 02 February 2019; published online 25 February 2019
Citation Ahmed Mahmood, Waheb A. Jabbar, et al., J. Nano- Electron. Phys. 11 No 1, 01011 (2019)
DOI https://doi.org/10.21272/jnep.11(1).01011
PACS Number(s) 00.00.60, 00.00.68
Keywords Ge- FinFET, Channel dimensions, ION/IOFF ratio, Subthreshold swing, MuGFET (2) .

Nano-electronic applications have benefited enormously from the great advancement in the emerging Nano-technology industry. The tremendous downscaling of the transistors’ dimensions has enabled the placement of over 100 million transistors on a single chip thus reduced cost, increased functionality and enhanced performance of integrated circuits (ICs). However, reducing size of the conventional planar transistors would be exceptionally challenging due to leakages electrostatics and other fabrication issues. Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate and a successor to conventional planar devices in nanoscale technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest of researchers in both academia and industry. However, aggressively scaling down of channel dimensions, will degrade the overall performance due to detrimental short channel effects. In this paper, we investigate the impact of downscaling of nano-channel dimensions of Germanium Fin Feld Effect Transistor (Ge-FinFET) on electrical characteristics of the transistor, namely; ION/IOFF ratio, Subthreshold Swing (SS), Threshold voltage (VT), and Drain-induced barrier lowering (DIBL). MuGFET simulation tool was utilized to conduct a simulation study to achieve optimal channel dimensions by considering channel length (L), width (W), and oxide thickness (TOX) individually. In addition, the effects of simultaneous consideration of all dimensions by exploiting a scaling factor, K was evaluated. According to the obtained simulation results, the best performance of Ge-FinFET was achieved at a minimal scaling factor, K  0.25 with 5 nm channel length, 2.5 nm width, and 0.625 nm oxide thickness.

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