Performance Enhancement of the Urdhva-Tiryagbhyam based Vedic Multiplier using FinFET

The demand for quick and effective real-time DSP ("Digital Signal Processing") applications has increased as a result of rapidly developing technologies. One of the fundamental mathematical processes that any application needs is multiplication. There are many uses for the Vedic Multiplier in the broad fields of image processing and DSP, notably the several variations of the original Vedic Multiplier topologies that improve speed and performance. The aim of a paper is to design the Vedic multiplier in MOSFET and FinFET technology and reduce the power and time of the design. For reducing the delay and power three different technology of adder is designed which are “GDI”, “Dual domino rail adder” and “Traditional adder”. The GDI technology has a better performance like lower power, delay and number of transistors so that using the GDI technology is used as the logic to design as full adder half adder and AND gate. To design the 2-bit multiplier it required four AND gate and two half adders to obtain the partial product. Later by using the 2-bit multiplier and 4-bit Ripple Carry Adder the 4-bit multiplier is mapped. Later using the 4-bit multiplier design the 8-bit multiplier is mapped. The proposed design is designed in MOSFET and FinFET technology as the result FinFET technology consume lower power and delay because of its lower leakage, higher drain current and higher performance. By using the FinFET technology overall performance will be 433.05 mW power and 0.981ns delay and MOSFET consumes 657.65 mW and 1.367 ns.