Power and Threshold Voltage Analysis of 14 nm FinFET 12T SRAM Cell for Low Power Applications
| Authors | P. Parthasarathi1, T.S. Arun Samuel1 , P. Vimala2, N. Arumugam1 |
| Affiliations |
1Department of ECE, National Engineering College, Kovilpatti, India 2Department of ECE, Dayananda Sagar College of Engineering, Bangalore, India |
| Е-mail | |
| Issue | Volume 14, Year 2022, Number 5 |
| Dates | Received 25 August 2022; revised manuscript received 20 October 2022; published online 28 October 2022 |
| Citation | P. Parthasarathi, T.S. Arun Samuel, P. Vimala, N. Arumugam, J. Nano- Electron. Phys. 14 No 5, 05008 (2022) |
| DOI | https://doi.org/10.21272/jnep.14(5).05008 |
| PACS Number(s) | 85.70. – w, 85.75. – d |
| Keywords | SRAM (4) , FinFET (16) , Power dissipation, BSIM4, Microwind. |
| Annotation |
Embedded SRAM units are required components in today's SoCs. Due to the increased popularity of portable battery-powered devices, low-power IC design has become a focus in recent years. Traditional SRAM cell designs are both power-hungry and underperforming in this new era of speedy mobile computing. This research focuses on the power dissipation of 14 nm FinFET 12T SRAM read and write operations at various temperatures. The power dissipation of the suggested SRAM cell was calculated and compared to that of various existing technologies. A BSIM4 model with a short channel is offered as the proposed 14 nm FinFET 12T SRAM cell. The proposed 12T SRAM power dissipation was 7.430 µw for reading and 12.278 µw for writing operations at 45 C. The recommended SRAM cell had a lower power dissipation. However, the threshold voltage was gradually reduced as the FinFET transistor was scaled down from 65 to 14 nm. For 14 nm FinFET simulations, the DSCH 3.8 and Microwind 3.8 tools were used. |
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