Current Transport Behaviour of Au/n-GaAs Schottky Diodes Grown on Ge Substrate With Different Epitaxial Layer Thickness Over a Wide Temperature Range
| Authors | N. Padha1 , R. Sachdeva1 , R. Sihotra1, S.B. Krupanidhi2 |
| Affiliations | 1 Department of Physics and Electronics, University of Jammu, Baba Sahib Ambedker Road, Jammu Tawi-180006, India 2 Materials Research Center, Indian Institute of Science, Bangalore 560012, India |
| Е-mail | nareshpadha@yahoo.com, sbk@mrc.iisc.ernet.in |
| Issue | Volume 3, Year 2011, Number 1, Part 5 |
| Dates | Received 04 February 2011, published online 08 December 2011 |
| Citation | N. Padha, R. Sachdeva, R. Sihotra, S.B. Krupanidhi, J. Nano- Electron. Phys. 3 No1, 926 (2011) |
| DOI | |
| PACS Number(s) | 85.30._z, 85.30.De, 85.30.Kk |
| Keywords | Ideality factor (10) , Barrier height (11) , Thermionic field emission, Tunneling (9) , Inhomogenities, Junction breakdown, Richardson constant. |
| Annotation |
The work presents temperature dependent forward and reverse current-voltage (I-V) analyses of n-GaAs/Au Schottky Diodes grown on n+ Ge substrate with different epitaxial layer thicknesses. While some of the Schottky diodes follow TED mechanism, others exceed significantly from this theory due to existence of patches of reduced barrier height embedded in the Schottky interface. The zero bias barrier heights (φbo) increase (0.649 to 0.809 eV) while the ideality factors (η) decrease (1.514 to 1.052) with increase in epitaxial layer thickness (1-4 μm), thus, indicating similar behaviour to that observed for the I-V characteristics of the undertaken Schottky diodes with decreasing temperature. It all indicated the existence of barrier inhomogenities over the M-S interface. The breakdown behaviour analysis of these diodes showed some interesting results; the breakdown voltage (VBR) decreases with temperature and shows ‘Defect Assisted Tunneling’ phenomenon through surface or defect states in the 1 μm thick epitaxial layer Schottky diode while VBR increases with temperature in 3 μm and 4 μm thick epitaxial layer Schottky diodes which demonstrate ‘Avalanche Multiplication’ mechanism responsible for junction breakdown. The reverse breakdown voltage is also seen to increase (2.7-5.9 Volts) with the increase in epitaxial layer thickness of the diodes. The undertaken diodes have been observed to follow TFE mechanism at low temperatures (below 200 K) in which the tunneling current component increases with epitaxial layer thickness which has been ascribed as an impact of GaAs/Ge hetero-interface over the Au/n-GaAs Schottky barrier. |
|
List of References |
Other articles from this number
1) Effect of Change in Ba Concentration on Crystallintiy and Dielectric Constant of the Sol-Gel Deposited Barium Strontium Titante (BST) Films on n-Type Si Wafer [0851-0858]2) Room Temperature Ammonia Gas Sensing Characteristics of Co3O4 [0859-0867]
3) A Two-Dimensional (2D) Potential Distribution Model for the Short Gate-Length Ion-Implanted GaAs Mesfets Under Dark and Illuminated Conditions [0868-0877]
4) Germanium Nanocrystals Embedded in Silicon Dioxide for Floating Gate Memory Devices [0878-0883]
5) Thermodynamic Properties of ZnO With in Mie-Grüneisen Hypothesis [0884-0887]
6) Numerical Simulation of Blinking Quantum dot Based on Temperature Dependence 3-Dimensional Levy Random Walk [0888-0893]
7) A 2-D Analytical Threshold Voltage Model for Symmetric Double Gate MOSFET's Using Green’s Function [0894-0902]
8) Absorption and Luminescence of Hydrogen and Oxygen Passivated Silicon Quantum Dots [0903-0909]
9) Surface States and Photoluminescence From Porous Silicon [0910-0913]
10) Manufacturing Practices for Silicon-Based Power Diode in Fast Recovery Applications [0914-0920]
11) Thermal Annealing Behaviour on Electrical Properties of Pd/Ru Schottky Contacts on n-Type GaN [0921-0925]
12) Role of Interface Charges on High-k Based Poly-Si and Metal Gate Nano-Scale MOSFETs [0937-0941]
13) Designing Single Chamber Hwcvd System for High Deposition Rate Device Quality A-Si:h Thin Films and Solar Cells [0942-0946]
14) High-k HfO2 Based Metal-Oxide-Semiconductor Devices Using Silicon and Silicon Carbide Semiconductor [0947-0955]
15) Antimony Doped Tin Oxide Thin Films: Co Gas Sensor [0956-0962]
16) A Doping Dependent Threshold Voltage Model of Uniformly Doped Short-Channel Symmetric Double-Gate (DG) MOSFET’s [0963-0971]
17) Gate Leakage Current Reduction With Advancement of Graded Barrier AlGaN/GaN HEMT [0972-0978]
18) Analytical Estimate of Open-Circuit Voltage of a Schottky-Barrier Solar Cell Under High Level Injection [0979-0991]
19) Variation of Quantum Well Infrared Photodetectors Parameter With an Applied Electric Field [0992-0994]
20) Barrier Inhomogeneities of Al/p-In2Te3 Thin Film Schottky Diodes [0995-1004]
21) Effect of Laser on the Bound Magnetic Polaron in a Semimagnetic Quantum Wire [1005-1009]
22) Propagation Characteristics of Surface Plasmon Waves on Au, Ag and Al at Optical Wavelengths [1010-1020]
23) Porous Silicon & Titanium Dioxide Coatings Prepared by Atmospheric Pressure Plasma Jet Chemical Vapour Deposition Technique-A Novel Coating Technology for Photovoltaic Modules [1021-1034]
24) Vacancy Defect Reconstruction and its Effect on Electron Transport in Si-C Nanotubes [1035-1040]
25) Simultaneous Effects of Hydrostatic Pressure and Geometry on Metal-Insulator Transition in a Cubical Quantum Dot [1041-1047]
26) Electrical Transport Characteristics of Pd/V/N-InP Schottky Diode From I-V-T and C-V-T Measurements [1048-1055]
27) Fabrication of Polyaniline/TiO~2 Nanocomposite Ammonia Vapor Sensor [1056-1063]
28) Structural, Optical, and Magnetic Properties of Zn1-xMnxs (x = 0.00, 0.01, and 0.03) Nanoparticles [1064-1070]
29) Modeling of Electron Mobility of GaN at Low Temperature and Low Electric Field [1071-1080]
30) Investigation of Implantation-Induced Damage in Indium Phosphide for Layer Transfer Applications [1081-1085]
31) Impact of Annealing on CuInSe~2 Thin Films and Its Schottky Interface [1086-1095]
32) Comparative Study of Polymer and Semiconductor for Fractional Quantum Hall Effect [1096-1101]
33) New Evolving Directions for Device Performance Optimization Based Integration of Compound Semiconductor Devices on Silicon [1102-1111]
34) Effect of Drift Region Doping and Coulmn Thickness Variations in a Super Junction Power MOSFET: a 2-D Simulation Study [1112-1119]
35) Effective Passivation of C-Si by Intrinsic A-Si:h Layer for hit Solar Cells [1120-1126]
36) Simulation and Optimization of n-Type PERL Silicon Solar Cell Structure [1127-1136]
