Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit
| Authors | K. Nehru, T. Nagarjuna, , G. Vijay |
| Affiliations | Department of Electronics and Communication, Institute of Aeronautical Engineering, Hyderabad, India |
| Е-mail | nnehruk@gmail.com, Nagarjuna473@gmail.com, Gpvijay24@gmail.com |
| Issue | Volume 9, Year 2017, Number 4 |
| Dates | Received 18 April 2017; published online 27 July 2017 |
| Citation | K. Nehru, T. Nagarjuna, , et al., J. Nano- Electron. Phys. 9 No 4, 04018 (2017) |
| DOI | 10.21272/jnep.9(4).04018 |
| PACS Number(s) | 85.30.Tv |
| Keywords | CNTFET (9) , ALU (7) , CMOS (18) , MOSFET (29) , Verilog, CPL. |
| Annotation | This paper proposes the novel low power and area efficient ALU (Arithmetic and Logic Unit) using adder and multiplexers. The adder and multiplexer are realized by using CNTFET (Carbon Nano Tube Field Effect Transistor) A verilog model of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in cadence spice software. The proposed ALU is simulated using Monte carlo simulation at 0.9 sub threshold voltage tested with 45 nm technology for the measurement of power and transistor counts. The power consumption of CNTFET based ALU is found to be 45.67 % better than the existing technologies. |
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