Design and Analysis of an Energy-Efficient Voltage Level Shifter for Low-Power Applications

Authors Pulyala Vasundhara, V. Shankar
Affiliations

Department of Electronics and Communication Engineering, G. Narayanamma Institute of Technology and Science (For Women) Shaikpet, 500104 Hyderabad, India

Е-mail vasundarareddy156@gmail.com
Issue Volume 18, Year 2026, Number 1
Dates Received 10 December 2025; revised manuscript received 15 February 2026; published online 25 February 2026
Citation Pulyala Vasundhara, V. Shankar, J. Nano- Electron. Phys. 18 No 1, 01020 (2026)
DOI https://doi.org/10.21272/jnep.18(1).01020
PACS Number(s) 84.30.Jc
Keywords Dual-supply, Level shifter, Differential cascade Voltage switch (DCVS), Subthreshold circuit, Low-power.
Annotation

This describes a low-energy voltage level shifter (LS) architecture. We further introduce a regulated cross-coupled (RCC) pull-up network to achieve a considerable reduction in dynamic power consumption with higher switching speed. The suggested LS can switch very low voltage signals below the input MOS device threshold up to the nominal supply voltage. A fast and very low power voltage level shifter (LS) is presented. By using a new regulated cross coupled (RCC) pull-up network, the switching speed is boosted and the dynamic power consumption is highly reduced. The proposed LS has the ability to convert input signals with voltage levels much lower than the threshold voltage of an MOS device to higher nominal supply voltage levels. The presented LS occupies a small silicon area owing to its very low number of elements and is ultra-low-power, making it suitable for low-power applications such as implantable medical devices and wireless sensor networks. Results of the post-layout simulation in a standard CMOS technology This LS is particularly appealing for low-power application fields, including implanted medical devices and wireless sensor networks, as it makes very little use of components and dissipation has been minimized. Benefiting from the use of sub-1V CMOS technology, it can convert as low input voltage level as 80 mV according to the post-layout simulation results. This LS gives the power dissipation of 123.1 nW with 23.7 ns propagation delay at supply voltages of 0.4/1.8 V (Low/High) and of input frequency of 1 MHz.

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