New Evolving Directions for Device Performance Optimization Based Integration of Compound Semiconductor Devices on Silicon

Authors Partha Mukhopadhyay1, Palash Das1, Edward Y. Chang2, Dhrubes Biswas1

1 Indian Institute of Technology, 721302, Kharagpur, India

2 National Chiao Tung University, Hsinchu, Taiwan

Issue Volume 3, Year 2011, Number 1, Part 5
Dates Received 04 February 2011, published online 08 December 2011
Citation Partha Mukhopadhyay, Palash Das, Edward Y. Chang, Dhrubes Biswas, J. Nano- Electron. Phys. 3 No1, 1102 (2011)
PACS Number(s) 73.40.Kp, 68.55.A –
Keywords Metamorphic buffer, Compound semiconductor, Integration, III-V/Si, Strain (10) , Dislocation density (4) , Lattice mismatch, Composite channel.
Rapid advances in Compound Semiconductor (CS) technologies over last several decades have lead to high performances in peak power, power added efficiency (PAE) and linearity, but these devices are not amenable for integration on mainstream silicon technologies. A strategic direction has been presented for the growth of CS devices on silicon with challenges abounding in scalability, compatibility and cost effectiveness while extracting optimized device performances. The approach at IIT Kharagpur has been simulation and experimental development of customized metamorphic buffers that are scalable and compatible to silicon without sacrificing any CS performances, primarily for electronic applications. This has evolved into a new strategic paradigm for performance optimization of seemingly competing and disparate properties which otherwise will not be supported by conventional process technologies. Simulation of these next generation structures reveals assimilation of superior device properties, with a novel five Indium content composite channel MHEMT indicating improvements over existing composite channel MHEMT in terms of linearity and higher current performances.

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