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Results (18):

Title Mechanically Stacked Triple-junction GaInP / GaAs / Si Solar Cell Simulation
Authors A.B. Gnilenko, S.V. Plaksin
Issue Volume 5, Year 2013, Number 4
Pages 04057-1 - 04057-6
Title An Analytical Universal Model for Symmetric Double Gate Junctionless Transistors
Authors N. Bora, P. Das, R. Subadar
Issue Volume 8, Year 2016, Number 2
Pages 02003-1 - 02003-4
Title Simulation of Guard Ring Type Effects on the Electrical Characteristics of n-on-p Planar Silicon Detectors
Authors M. Mekheldi,, S. Oussalah, A. Lounis, N. Brihi
Issue Volume 11, Year 2019, Number 4
Pages 04008-1 - 04008-6
Title Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip
Authors S. Nanda, R.S. Dhar
Issue Volume 13, Year 2021, Number 3
Pages 03015-1 - 03015-4
Title Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications
Authors Ritam Dutta, Nitai Paitya
Issue Volume 13, Year 2021, Number 3
Pages 03020-1 - 03020-4
Title Impact of High-k Dielectric Materials on Short Channel Effects in Tri-gate SOI FinFETs
Authors Zohmingmawia Renthlei, Swagat Nanda, Rudra Sankar Dhar
Issue Volume 13, Year 2021, Number 5
Pages 05013-1 - 05013-6
Title Improvement Analysis of Leakage Currents with Stacked High-k/Metal Gate in 10 nm Strained Channel HOI FinFET
Authors Payal Kumari, Swagat Nanda, Priyanka Saha, Rudra Sankar Dhar
Issue Volume 14, Year 2022, Number 2
Pages 02004-1 - 02004-4
Title Performance Analysis of Incorporating a Buried Metal Layer in a Junction-Less Multi-Channel Field Effect Transistor
Authors S. Ashok Kumar, A. Roshan Solomon, T. Thirumurugan, S. Dhanraj
Issue Volume 15, Year 2023, Number 2
Pages 02007-1 - 02007-4
Title Performance Analysis of Charge-plasma Based Doping less Nanowire Field Effect Transistor
Authors P. Raja, P. Naveen Chander, B. Mohamed Faisal, V. Prakash
Issue Volume 15, Year 2023, Number 3
Pages 03031-1 - 03031-3
Title Analysis of Charge Plasma Based Hetero Junction Nanowire Multi Channel Field Effect Transistor for Sub 10 nm
Authors M. Balaji, S. Ashok Kumar
Issue Volume 15, Year 2023, Number 4
Pages 04032-1 - 04032-4
Title Repercussions Through Inclusion of Multi Bridge Channels into Gate All Around Nano-Wire Field Effect Transistor
Authors S. Ashok Kumar, J. Soundararajan, P. Mahendra Peruman, J. Susmitha, K. Krishnaprasath
Issue Volume 15, Year 2023, Number 5
Pages 05019-1 - 05019-4
Title High Power Analysis of Surrounded Channel Junction Less Field Effect Transistor
Authors N. Das , K.C.D. Sarma
Issue Volume 16, Year 2024, Number 5
Pages 05004-1 - 05004-4
Title Resistance Based Drain Current Model of Surrounded Channel Junction Less Field Effect Transistor
Authors N. Das , K.C.D. Sarma
Issue Volume 16, Year 2024, Number 4
Pages 04002-1 - 04002-5
Title Graphene Nanoribbon Based Asymmetric Tunnel FET for Fast Switching and Low Power Applications
Authors R. Dutta, D. Das, R. De
Issue Volume 17, Year 2025, Number 3
Pages 03014-1 - 03014-5
Title An Analytical Method for Determination of Threshold Voltage of Surrounded Channel Junctionless Field Effect Transistor
Authors N. Das , K.C.D. Sarma, R. Swargiary
Issue Volume 17, Year 2025, Number 5
Pages 05008-1 - 05008-4
Title Leveraging Gate and Channel Engineering in Graphene Tunnel FET (GTFET) at Nano-Scale for Better Device Performance
Authors R. Dutta, D. Das
Issue Volume 18, Year 2026, Number 2
Pages 02012-1 - 02012-5
Title TCAD Driven Light-Trapping Enhancement in Silicon Photovoltaics through Engineered Nanohole Geometries
Authors Monika Gogoi, T.D. Das
Issue Volume 18, Year 2026, Number 2
Pages 02028-1 - 02028-5
Title Impact of Hole Density on Sub-10 nm SOI Trigate MOSFET Using Charge Plasma Technique with Circuit-Level Analysis
Authors S.A. Kumar, J. Prabhu G, V. Sandeep, J. Soundararajan
Issue Volume 18, Year 2026, Number 2
Pages 02031-1 - 02031-5