A Novel Energy-Efficient Approach for RT-Free TSPC Dual-Edge Triggered Flip-Flops Using STC
| Authors | Krishna Kishore Gudimella, Ramya Surupanga, Mehnaaz Jabeen |
| Affiliations |
Department of Electronics and Communication Engineering, G. Narayanamma Institute of Technology and Science (For Women) Shaikpet, Hyderabad-500104, India |
| Е-mail | kishore@gnits.ac.in |
| Issue | Volume 17, Year 2025, Number 6 |
| Dates | Received 25 July 2025; revised manuscript received 12 December 2025; published online 19 December 2025 |
| Citation | Krishna Kishore Gudimella, Ramya Surupanga, Mehnaaz Jabeen, J. Nano- Electron. Phys. 17 No 6, 06022 (2025) |
| DOI | https://doi.org/10.21272/jnep.17(6).06022 |
| PACS Number(s) | 07.50.Ek, 84.30. – r |
| Keywords | DET (14) , Low power consumption, PDP (2) , Flip-flop. |
| Annotation |
Power consumption reduction in both static and dynamic forms is essential in digital circuits, especially in clocking networks and flip-flops used in GPUs and AI processors. Dual-edge-triggered flip-flops (DET-FFs) improve efficiency by capturing data on both clock edges, enabling lower clock frequency operation and reducing dynamic power consumption. However, conventional DET-FFs suffer from excessive switching activity and redundant transitions, leading to unnecessary power dissipation. To address this, a Single-Transistor-Clocked Dual-Edge-Triggered Flip-Flop (STC-DET-FF) is proposed, integrating True Single-Phase Clocking (TSPC) with Single-Transistor-Clocked Buffers (STCBs) to eliminate redundant transitions and optimize power efficiency. Designed using 32 nm CMOS technology, the STC-DET-FF is evaluated based on power consumption, propagation delay, and Power-Delay Product (PDP). Simulation results show that the proposed design achieves a significant reduction in power consumption, outperforming FN_C-DET by 14 % at 0.4 V and 9.5 % at 0.8 V. Additionally, it exhibits the lowest PDP of 0.6879 fJ, which is a major improvement compared to FN_C-DET (4.364 fJ) and TGFF (8.807 fJ). These results demonstrate the STC-DET-FF’s effectiveness in minimizing power dissipation while maintaining performance, making it a viable solution for low-power and high-performance computing applications. |
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