Nano-Scale Patterning of Silicon Nanoparticles on Silicon Substrate by DIP-PEN-Nanolithography

Authors A. Kumar1 , P.B. Agarwal1 , S. Sharma2, D. Kumar2

1 Central Electronics Engineering Research Institute, Pilani – 333 031, India

2 Department of Electronics Science, Kurukshetra University, Kurukshetra – 136 119, India

Issue Volume 3, Year 2011, Number 1, Part 1
Dates Received 04 February 2011, in final form 18 March 2011, published online 23 March 2011
Citation A. Kumar, P.B. Agarwal, S. Sharma, D. Kumar, J. Nano- Electron. Phys. 3 No1, 127 (2011)
PACS Number(s) 81.16.Nd, 68.37.Ps
Keywords Dip-pen nanolithography, Self-assembled-monolayers (2) , AFM (18) , Silicon nanoparticles (2) , Nanopatterning (2) , Nanoelectronics (3) .
Dip-Pen Nanolithography technique has been used to write nano-scale patterns of silicon nanoparticles on Si/SiO2 substrate using commercially available silicon nanoparticles suspension as ink (mean diameter 30 nm). Patterning experiments have been carried out under varying process conditions namely, temperature and humidity with varying writing speed. Linewidth of 92 nm has been measured at writing speed of 0.1 μm/sec, which reduced to 54 nm at higher speed of 1.6 μm/sec. Obtained results would be useful for patterning nano-size features of other hard materials (semiconductors and metals) for applications in nanoelectronics and biotechnology.

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