Effect of Grain Size on the Threshold Voltage for Double-Gate Polycrystaline Silicon MOSFET
| Автори | Mahesh Chandra1, Alka Panwar2, B.P. Tyag1 |
| Приналежність | 1 D B S (Post Graduate) College, Dehradun - 248001, India 2 Chinmhaya College of Sciences, Haridwar, India |
| Е-mail | maheshc059@gmail.com |
| Випуск | Том 3, Рік 2011, Номер 1, Part 3 |
| Дати | Received 04 February 2011, published online 22 June 2011 |
| Посилання | Mahesh Chandra, Alka Panwar, B.P. Tyag, J. Nano- Electron. Phys. 3 No1, 474 (2011) |
| DOI | |
| PACS Number(s) | 85.30 De |
| Ключові слова | Double gate poly silicon MOSFET, Grain size and threshold voltage. |
| Анотація |
The effect of grain size (D) on the threshold voltage (Vth) for double gate polycrystalline silicon MOSFET is investigated theoretically in terms of grain boundary trap states (NT). It is found that the threshold voltage (Vth) increases non-linearly with increasing silicon-oxide thickness (tox) for all values of grain size (D). However the threshold voltage is seen to have smaller values for same tox for the larger grains. This may be attributed to the reduction in the number of trap states in the depletion regions on either side of a grain boundary. Finally the dependence of threshold voltage (Vth) on various parameters such as the doping concentration, interface trap state density and field penetration from drain to source are explored out. The results of these findings are in good agreement with those available in the literature. For large grain poly silicon MOSFET the threshold voltage is seen to approach the single crystal value. |
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