Numerical Simulation of FinFET Transistors Parameters

Автор(ы) І.P. Buryk1, A.O. Golovnia1, M.M. Ivashchenko1, L.V. Odnodvorets2
Принадлежность

1Konotop Institute of Sumy State University, 24, Myru Ave., 41615 Konotop, Ukraine

2Sumy State University, 2, Rymsky-Korsakov St., 40007 Sumy, Ukraine

Е-mail
Выпуск Том 12, Год 2020, Номер 3
Даты Received 03 February 2020; revised manuscript received 15 June 2020; published online 25 June 2020
Ссылка І.P. Buryk, A.O. Golovnia, M.M. Ivashchenko, L.V. Odnodvorets, J. Nano- Electron. Phys. 12 No 3, 03005 (2020)
DOI https://doi.org/10.21272/jnep.12(3).03005
PACS Number(s) 85.30.De, 85.30.Tv, 73.40.Qv
Ключевые слова SOI TG FinFET, Short-channel effects (2) , Effective work function, Threshold voltage (15) , High-k dielectric (2) .
Аннотация

Complementary afin field-effect transistors FinFET with high parameter stability and low power consumption are used as power supplies, amplifiers, frequency converters in sensors and electronic equipment, as well as high-frequency switching generators and modulators in medical devices for welding biological tissues. Results of 3D numerical simulation of p- and n-types of SOI TG FinFET transistors are presented. The structure of 3D devices based on SOI (Silicon-On-Insulator) technology with TRI-GATE (TG) shutter is described and modeled using SILVACO TCAD tools. The current-voltage characteristics have been constructed, and allowable values of leakage current and threshold voltage of n- and p-transistors with gate electrodes have been calculated on the basis of film systems with effective outputs of 4.40 eV and 4.85 eV. The implementation of multi-gate film electrodes based on Ni and Ta is essential for the digital design of ultra-large integrated circuits (VLSI). The simulation results allow us to determine the permissible values of the threshold spread, the DIBL, the leakage current, and the coefficient Ion/Ioff. The basis of the design of transistor structures is to study the operating parameters of the transistor in the open state and the geometric dimensions of the individual structural elements. These results may be used for designing the 3D CMOS transistors

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