Analytical Modeling & Simulation of OFF-State Leakage Current for Lightly Doped MOSFETs

Author(s) Nitin Sachdeva1, Munish Vashishath1, P.K. Bansal2
Affiliations

1 YMCA University of Science & Technology, Faridabad, India

2 Malout Institute of Management & Information Technology, Malout, India

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Issue Volume 9, Year 2017, Number 6
Dates Received 20 May 2017; revised manuscript received 15 November 2017; published online 24 November 2017
Citation Nitin Sachdeva, Munish Vashishath, P.K. Bansal, J. Nano- Electron. Phys. 9 No 6, 06009 (2017)
DOI 10.21272/jnep.9(6).06009
PACS Number(s) 85.30.Tv
Key words MOSFET (18) , SS (131) , Threshold voltage (15) , SCEs (3) .
Annotation Prior to the fabrication of Integrated circuits, the electrical parameters are analytically modeled & simulated using any computer aided design tool. The ever increasing demand of the features of the electronic appliances has forced to put more and more transistors in a small IC chip. The main target of the integrated circuit design and fabrication is to achieve more functionality at higher speed using less power, less area and low cost. Various parameters like threshold voltage, sub-threshold leakage current and sub-threshold slope etc. are analytically derived and simulated to get match with each other. In this paper, 45 nm n-channel metal-oxide- semiconductor field effect transistor (NMOS) has been designed in SILVACO tool to give low off state leakage current by increasing the work function of gate.

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